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https://github.com/naivecynics/Computer_Orgnization_Project.git

0. Directory

1. Developers Information

（1）Contribution Ratio

WYT 吴雨潼 12213012 3Mker 33.3% QKT 秦恺通 12212606 IRONMAN1024 33.3% HLC 黄朗初 12213009 naivecynics 33.3%

（2）Directory Catalog

.(git)
├── README.md
├── .gitignore                  // ignore ip core configuration files
│                               // instruction PDFs
├── CPU大作业测试说明.pdf
├── Computer Orgnization大作业-cs202-release.pdf
├── Ego1_UserManual_v2.2.pdf
├── Minisys硬件手册1.1.pdf
├── RISC-V-Reference-Data.pdf
│
├── Schematic.png               // Schematic of the project
├── Design_DIagram.jpg          // Reference design diagram
│
├── constrs_1                   
│   └── new
│       ├── eg01.xdc            // eg01 constrs file
│       └── minisys.xdc         // minisys constrs file
├── new
│   │                           // cpu core module
│   ├── ALU.v
│   ├── cpu_top.v
│   ├── data_memory.v
│   ├── datapath.v
│   ├── ecall_controller.v
│   ├── imm_gen.v
│   ├── instr_decoder.v
│   ├── main_controller.v
│   ├── parameters.v
│   ├── pc.v
│   ├── reg_file.v
│   │   
│   ├── hardware_top            // hardware top module
│   │   ├── PS2.v
│   │   ├── debounce.v
│   │   ├── hardware_top.v
│   │   ├── keyboard_debouncer.v
│   │   ├── keypad_minisys.v
│   │   ├── process_keyboard.v
│   │   └── tube.v
│   │   
│   ├── assemble                // assemble test code
│   │   ├── lastest.asm
│   │   ├── scene1.asm
│   │   ├── scene2.asm
│   │   └── text_to_coe.py
│   │   
│   ├── bin_to_coe              // final bitstream
│   │   ├── a_tailed_risc-v_CPU_CSE.bit
│   │   ├── final_1.0.bit
│   │   ├── test1.bit
│   │   └── test2.bit
│   │   
│   ├── tools                   // toolchains
│   │   ├── bin_to_coe.py       // any base to coe 
│   │   ├── coe_to_uart_txt.py  // coe to uart txt
│   │   ├── riscv32_to_coe.sh   // linux riscv32 to coe
│   │   ├── scene1.asm
│   │   ├── scene1.coe
│   │   ├── scene1.txt
│   │   ├── scene2.asm
│   │   ├── scene2.coe
│   │   ├── scene2.txt
│   │   ├── scene2_keyboard.asm
│   │   ├── scene2_keyboard.coe
│   │   └── scene2_keyboard.txt
│   │   
│   └── uart                    // uart tools and txt
│       ├── GenUBit_RISC_V.bat
│       ├── UartAssist.exe
│       ├── rars2coe.exe
│       ├── scene1.txt
│       ├── scene2.txt
│       └── scene2_keyboard.txt
└── sim_1                       // simulation files
│   └── new
│       ├── controller_tbc.v
│       ├── cpuclk_tbc.v
│       ├── keypad_tbc.v
│       ├── top_tbc.v
│       └── tube_tbc.v
└── END

2. Development Github Log

$ git log --graph --pretty=format:"%h - %an, %ad : %s" --abbrev-commit --date=short

* cfbbe33 - naivecynics, 2024-06-03 : final
* 0b85c8c - naivecynics, 2024-06-03 : final wind up
* 9ad3ec2 - IRONMAN1024, 2024-06-02 : update
* a19269c - naivecynics, 2024-06-02 : ecall +1
* c6c2c0b - IRONMAN1024, 2024-05-27 : qkt111
* 7178d68 - IRONMAN1024, 2024-06-01 : uart_top
* f5d6612 - naivecynics, 2024-06-01 : keyboard debug
* b10839c - 3Mker, 2024-05-31 : update
* 61ebb2d - Langchu Huang, 2024-05-31 : GNU toolchain added
* f7529a5 - 3Mker, 2024-05-27 : update
* d7eefa7 - 3Mker, 2024-05-27 : update
* 818ab03 - naivecynics, 2024-05-27 : block ecall signal
* 5ec146b - 3Mker, 2024-05-27 : update
* e0b856e - 3Mker, 2024-05-24 : wytnew
* 6b8039e - 3Mker, 2024-05-24 : wyt
* 5f8d2a8 - naivecynics, 2024-05-27 : update so many things
* 6aa1991 - naivecynics, 2024-05-24 : all
* 5f49526 - naivecynics, 2024-05-22 : beq_debug_passed
* 7903d8e - naivecynics, 2024-05-22 : hlc_pc_ecall
*   79de483 - 3Mker, 2024-05-22 : Merge branch 'master'
|\\  
| * 34583b7 - naivecynics, 2024-05-19 : update
| * eefa048 - naivecynics, 2024-05-19 : hardware drive
* | ef86eef - 3Mker, 2024-05-22 : wyt update
|/  
* 044aab3 - 3Mker, 2024-05-19 : preliminary
* 803806d - IRONMAN1024, 2024-05-17 : modified
* 7ffa890 - IRONMAN1024, 2024-05-15 : update
* 3159544 - IRONMAN1024, 2024-05-15 : i_fetch
*   9f38ff1 - 3Mker, 2024-05-15 : Merge branch 'master'
|\\  
| * 4ed4f12 - Langchu Huang, 2024-05-15 : debug: executable
| * 429350b - Langchu Huang, 2024-05-15 : add gitignore
| * d696e3c - Langchu Huang, 2024-05-13 : supplement
| * aae18a1 - naivecynics, 2024-05-13 : 1.ip setting 2. compile passed 3. add instr mem
* | e58b73e - 3Mker, 2024-05-15 : asm
* | 2fe8b4c - 3Mker, 2024-05-15 : add asm sample
|/  
*   0530bc9 - 3Mker, 2024-05-12 : Merge branch 'master' 
|\\  
| * 209217f - IRONMAN1024, 2024-05-12 : datapath finish!
| * e65fdf4 - IRONMAN1024, 2024-05-12 : PC
* | 603b2dc - 3Mker, 2024-05-12 : update_decoder
|/  
* 0a1e25c - naivecynics, 2024-05-12 : 7tube
* 176f4c7 - naivecynics, 2024-05-12 : update
* f84d546 - naivecynics, 2024-05-12 : updatae
*   4f75181 - 3Mker, 2024-05-12 : Merge branch 'master' 
|\\  
| * 75b0698 - IRONMAN1024, 2024-05-07 : ALU
* | 79f601c - 3Mker, 2024-05-12 : update
|/  
* ab2d3d2 - naivecynics, 2024-05-06 : ip core
* ba0e660 - naivecynics, 2024-04-29 : add readme
* 236aa23 - naivecynics, 2024-04-29 : delete trash
* 138b17c - naivecynics, 2024-04-29 : previous cpu design

3. CPU Architecture Design

（1）CPU Information Card